UROP Project

Energy-efficient Mapping of Neural Networks to Hardware



Daniel Holder

Program Director UROP


+49 241 80-90695


Key Info

Basic Information

Project Offer-Number:
UROP International
Electrical Engineering, Information Technology and Computer Engineering
Organisation unit:
Chair of Integrated Digital Systems and Circuit Design
Language Skills:


Algorithms inspired by the human brain have become an important focus of research in the past years. The areas of data processing and computational neuroscience have both profited from algorithms built on simple models of the biological neuron. While artificial models required by the Machine Learning community have been increasing in terms of storage, energy and area requirements over the past few years in order to reliably classify ever more complex datasets, energy-efficient algorithms and hardware architectures are an inherent challenge of modeling biological neural networks at the scale of the human brain, as required by scientists and engineers in the domain of computational neuroscience. The development of dedicated hardware platforms offers a cost-effective solution to tackle these requirements.


Current research projects at our institute include the development of an ASIC platform for ECG signal classification, studies on energy-efficient software-to-hardware mappings of CNNs (e.g. using sophisticated quantization techniques) and the conception of a new computing architecture for the accelerated simulation of biological neural networks. The details of your project will be refined based on your prior experience in software and/or hardware development and your personal interests. In general, you will work in either the domains of algorithmic research, the software-to-hardware mapping of reference models or pure hardware development, in one of the research areas specified above.


Research-oriented mindset, high intrinsic motivation, self-starter, team oriented; Hands-on experience in Python, C++ and/or Matlab (at least one); Coding and design-flow experience (FPGA, ASIC) is a plus (depending on project) - Knowledge in either artificial (CNNs, LSTMs, etc.) or biological neural networks is a plus