A Step Towards Next-Generation Neuroscience Simulators

07/06/2023

Contact

Phone

work
+49 241 80-97600

Email

E-Mail

The group of Tobias Gemmeke at RWTH Aachen University has developed a highly flexible framework neuroAIˣ

 

Despite decades of research, the brain remains to a large extent a mystery and the basic question of how the brain processes information is still a puzzle. This is a fundamental question not only for neuroscience and medicine, but also for engineers and computer scientists, who are increasingly taking inspiration from the brain to improve the architecture and performance of computers.

To answer this question, neuroscientists focus on studying groups of neurons – so-called microcircuits – and the interplay of small brain areas. By investigating how individual neurons work together to form circuits and to perform complex tasks, neuroscientists develop models to explain how the brain processes information and – at an increasing the level of complexity – how behavior emerges from the activity of the neurons. Computer simulations of neural network models play a crucial role in this type of investigation.

Simulating biological neural networks is, however, a hard challenge. Classic high-performance computers or GPU clusters are not well suited to execute such simulations, while dedicated hardware solutions face a chicken-and-egg problem: as our understanding of neural circuits is growing and becoming more elaborated, so do the requirements placed on the simulator change. The team of Prof. Tobias Gemmeke, Chair for Integrated Digital Systems and Circuit Design at RWTH Aachen University, has developed a framework that responds exactly to the need of developing a fast and efficient neuroscience simulator, while maintaining a high degree of architectural flexibility, able to adjust to the progress in the field. “As a neuroscientist I am excited. The progress reported here is breathtaking. Simulations much faster than realtime are essential for investigations of plasticity and learning unfolding over hours and days.” says Markus Diesmann, director and neuroscientist at the FZ Jülich.

The framework, which has been named neuroAIˣ, is composed of a software tool for quickly assessing novel neuromorphic architectures, and a by hardware cluster currently formed by 35 Field-Programmable Gate Array (FPGA ) boards. The FPGA cluster has a double function: on one hand, it serves as testbed to calibrate the software tool and to empirically test the efficiency of the proposed architectures. On the other hand, it is itself a fully functional neuroscience simulator, which surpasses by a factor 10 the best platforms available today both in terms of speed and energy efficiency.

“We are pleasantly surprised by the high acceleration and the energy efficiency achieved by our system, because the focus of our work was on flexibility and reproducibility of the simulator system.”, explains Kevin Kauth, a PhD student in the group of Gemmeke and one of the main developers in the project.

The efficiency and speed of the FPGA cluster go hand in hand, and both result from the fact that it has been designed exploiting known neuromorphic principles. “The capabilities of modern-day artificial intelligence (AI) are shooting through the roof – as is the energy consumed in computing hardware. Humanity badly needs to take inspiration from biology to conceive sustainable ways of realizing “smart” computations,” says Prof. Gemmeke. The high energy efficiency of the realized FPGA cluster holds good promises that bio-inspired computing architecture can help mitigating the carbon footprint of future AI.

The FPGA cluster can be also used to explore neuromorphic architectures based on novel memristive devices, such as those researched in the projects Neurotec and NeuroSys – two major initiatives funded by the German Ministry of Education and Research (BMBF) for developing next-generation neuromorphic hardware. Memristors (the name is a contraction of “memory resistor”) are passive circuit elements whose resistance can be programmed by applying an external voltage. This feature makes them ideal candidates to develop the hardware-analog of synapses, and holds great promises for boosting the performance of neuromorphic hardware. The flexibility of the neuroAIˣ framework can facilitate the co-design of software and hardware based on these novel devices by emulating the behavior of novel electronic devices on the FPGAs.

Gemmeke and colleagues are now considering realizing an upscaled version of the FPGA cluster and a web interface to provide cloud-access to the cluster to neuroscientists and AI researchers around the world.
A detailed description of the neuroAIx framework has been reported in the open-access journal Frontiers in Computational Neuroscience.