MNEMOSENE

  This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 780215.  

Title

Computation-in-memory architecture based on resistive devices

Concept

The MNEMOSENE project aims at demonstrating a new computation-in-memory (CIM) based on resistive devices together with its required programming flow and interface. To develop the new architecture, the following scientific and technical objectives will be targeted:

• Objective 1: Develop new algorithmic solutions for targeted applications for CIM architecture.
• Objective 2: Develop and design new mapping methods integrated in a framework for efficient compilation of the new algorithms into CIM macro-level operations; each of these is mapped to a group of CIM tiles.
• Objective 3: Develop a macro-architecture based on the integration of group of CIM tiles, including the overall scheduling of the macro-level operation, data accesses, inter-tile communication, the partitioning of the crossbar, etc.
• Objective 4: Develop and demonstrate the micro-architecture level of CIM tiles and their models, including primitive logic and arithmetic operators, the mapping of such operators on the crossbar, different circuit choices and the associated design trade-offs, etc.
• Objective 5: Design a simulator (based on calibrated models of memristor devices & building blocks) and FPGA emulator for the new architecture (CIM device combined with conventional CPU) in order demonstrate its superiority. Demonstrate the concept of CIM by performing measurements on fabricated crossbar mounted on a PCB board.

Participants

• Technische Universiteit Delft, Netherlands (Coordinator)
• Technische Universiteit Eindhoven, Netherlands
• Institut national de recherche en informatique et automatique, France
• Eidgenössische Technische Hochschule Zürich, Switzerland
• Stichting IMEC Nederland, Netherlands
• ARM Limited, United Kingdom
• IBM Research GmbH, Switzerland
• Intelligentsia Consultants Sàrl, Luxembourg